In deep submicron technology, worst process conditions and voltage scaling has created many problems in SRAM memories. Write failure in an SRAM memory cell is one critical problem caused due to the above reasons.
During a read operation, the pass transistor and the on NMOS driver act as voltage divider which raises the level of a zero stored in the memory cell. If the driver transistor resistance is comparable to the pass transistor resistance, then the raised internal node level can trip the memory cell in the opposite direction and thus the data will be corrupted. So for a non-destructive memory cell read, the pass transistors' resistance is made more than that of the driver transistors. This leads to further degrading of writability and the write time of the memory cell, because now a high voltage swing is required across BL/BLB for raising the level of the stored zero. This makes the writability issue even more of a concern at very low voltages.
Existing SRAM memory cells have extremely low voltage power supply requirements. Power supply requirements can range from 0.9 volts to 1.3 volts. At these low voltage levels, SRAM cell designs are tuned for ensuring margins but the writability of the memory cell is major problem. To make the SRAM memory cell writable at low voltages, write boost must be implemented. A write boost circuit is also required to address a process corner wherein NMOS transistors are slow and PMOS transistors are fast. To successfully cater to the above needs a new write boost circuit is required, which assures the writability at a particular process corner and in the low voltage power supply range in order to reduce boost power
A conventional SRAM memory cell 100 is shown in which the basic six-transistor cell includes transistors MPG1, MPG2, MPU1, MPU2, MPD1, and MPD2. Transistor MPG1 is coupled to the bit line BL, and transistor MPG2 is coupled to the inverting bit line BLB. Transistors MPU1 and MPU2 are coupled to VDD through an upper power terminal, and transistors MPD1 and MPD2 are coupled to ground through a lower power terminal. As is known in the art, a P-channel precharge circuit and an N-channel input circuit are coupled to the bit lines BL and BLB.
In the conventional memory cell 100, there is word line WL, which activates the memory cell read/write operation through the gates of transistors MPG1 and MPG2. The precharge block is for precharging BL/BLB after a read/write operation, and the write driver NMOS transistor is used to pull down BL/BLB in a write operation. In/Inb are data inputs used to write a zero or one, depending on the data logic input.
Different prior art methods are known to improve writability at low voltages. Ground raising is one the them. Writability is a problem at a slow NMOS and fast PMOS process corner. Raising GND at other process corners only increases the boost power where write boost is not required. At high power supply voltage ranges the write boost is not required, which otherwise will increase the dynamic power as boost power will be extra power consumed. So to control write boost at low voltages external pins are used, which are manually controlled by the user.
A first known prior art technique is shown in U.S. Pat. No. 5,396,469. The advantages of this technique is that the GND level is raised during the write operation, and thus writability will improve. The disadvantages of this technique are that the GND of the complete row is raised, which reduces the signal to noise margin of unselected MUX columns of the same row. Also, GND is raised for both the NMOS drivers of a single memory cell (ON and OFF). This limits writability and write time to some extent as the off NMOS is now going to be on after the write operation is supplied with a raised GND.
A second known prior art technique is shown in US Publication No. 2006/0171188A1. The advantage of this technique is that VDD is lowered during the write operation, and thus writability will improve. The disadvantages are that the VDD lowering/cut off is implemented for both PMOS transistors simultaneously. This limits writability and write time to some extent as the off PMOS transistor, which is now going to be on after the write operation, is supplied with a lowered VDD voltage. If VDD is shared along the column then retention noise margin for memory cells in that same column will be reduced.
Write boost for SRAM is required in deep submicron technologies and also at low supply voltages in all technologies. This boost is required below a particular supply voltage of operation and also for a particular process corner. Presently used methods provide assists across all process corners with voltage dependent operation mode controlled externally. Thus, a need remains for a write boost circuit suitable for an SRAM that provides the desired extra performance required for low voltage and specific process corner operation, while addressing the problems associated with the prior art solutions.